The invention relates to a method of fabricating integrated circuits, in which during this method an integrated circuit configuration is fabricated on a semiconductor wafer and in which conductor tracks, which are required for test purposes and which can be severed, are fabricated, which tracks each have two conductor track sections which issue from the integrated circuit configuration.
The invention further relates to an integrated circuit having an integrated circuit configuration and including two conductor track sections, which issue from the integrated circuit configuration and which form parts of a conductor track required for test purposes during the fabrication of the integrated circuit and forming a severed conductor track after the fabrication.
A method as defined hereinbefore and an integrated circuit as defined hereinbefore are known from the patent document DE 42 00 586 A1. The known integrated circuit fabricated with the aid of the known method has the problem that in the finished integrated circuit the two conductor track sections, which in the first place constitute portions of a previously severed conductor track, which conductor track is frequently referred to as a saw bow in the technical jargon, and which in the second place issue from the relevant integrated circuit configuration of the integrated circuit, and which in the third place each extend up to a bounding surface of a semiconductor die carrying the integrated circuit configuration, and which in the fourth place are required for the application of a useful signal used for test purposes during the fabrication of the integrated circuit, are simply accessible. An undesired consequence of this simple accessibility is that it is possible to make an electrically conductive connection between the two conductor track sections by means of a conductive material, for example by means of a conductive adhesive or a conductive liquid or a conductive solder joint, as a result of which the conductor track originally required for test purposes, i.e. the so-called saw bow, is afterwards replaced with a substitute electrically conductive connection in an undesirable manner. However, this enables said substitute electrically conductive connection provided as a replacement to be utilized for the application of a useful signal for test purposes. Thus, an unauthorized person can afterwards illegally carry out at least a test operation on an integrated circuit that has been fabricated by the authorized manufacturer of the known integrated circuit and has been deactivated for test purposes, which entails the risk and the possibility that, inter alia, also access is obtained to protected data stored in the integrated circuit, which data should actually be available only during a test operation to be carried out by the authorized manufacturer.
It is an object of the invention to preclude the aforementioned problems and to realize an improved method of fabricating integrated circuits and an improved integrated circuit in a simple and cost-effective manner.
In order to achieve the aforementioned object, characteristic features have been provide in a method in accordance with the invention, in such a way that a method in accordance with the invention may be characterized in the manner defined hereinafter, namely:
A method of fabricating integrated circuits, in which a reticular pattern of separation strips on the semiconductor wafer is defined, and in which a plurality of juxtaposed integrated circuit configurations are formed between the separation strips on the semiconductor wafer, and in which during the fabrication of the integrated circuits at least one conductor track required for test purposes is formed for each integrated circuit, which conductor track has two conductor track sections, which two conductor track sections issue from the relevant integrated circuit configuration and each extend at least into a separation strip and are connected to one another in an electrically conductive manner in the areas of their ends which are remote from the integrated circuit configuration, and which conductor track serves for the application of a useful signal utilized for test purposes, and in which during the fabrication of the integrated circuits for each integrated circuit at least one additional conductor track section is formed adjacent a conductor track section, which additional conductor track section issues from the relevant integrated circuit configuration and extends toward a separation strip and serves for applying a spurious signal which interferes with testing, and in which after the fabrication of the integrated circuits on the semiconductor wafer the semiconductor wafer is partitioned into semiconductor dice along the separation strips, during which the conductor tracks are severed.
Moreover, in order to achieve the aforementioned object, characteristic features have been provide in an integrated circuit in accordance with the invention, in such a way that an integrated circuit in accordance with the invention may be characterized in the manner defined hereinafter, namely:
An integrated circuit having the means defined hereinafter, namely: a semiconductor die, which is bounded by bounding faces, and an integrated circuit configuration realized on the semiconductor die and situated within the bounding faces, in which two conductor track sections have been provided, which two conductor track sections issue from the integrated circuit configuration and each extend up to a bounding face and were required for the application of a useful signal utilized for test purposes during the fabrication of the integrated circuit, and in which at least one additional conductor track section has been provided, which at least one additional conductor track section is disposed adjacent a conductor track section and issues from the integrated circuit configuration and extends toward a bounding surface and serves for the application of a spurious signal which interferes with testing.
The major advantage obtained with a method in accordance with the invention and an integrated circuit in accordance with the invention is that, in the case that in an unauthorized manner the two conductor track sections of the conductor track originally required for test purposes, i.e. the so-called saw bow, are electrically interconnected by means of an electrically conductive material, not only the two conductor track sections of the conductor track originally required for test purposes are electrically interconnected but, in addition, at least one additional conductor track section is electrically connected to the two conductor track sections in the form of a short-circuit. This has the advantage that, in the case of an attempt to carry out an unauthorized test operation via the substitute connection made with the aid of an electrically conductive material, not only the useful signal employed for test purposes but also the spurious signal, which interferes with testing, is applied. As a result of this, an evaluation of the useful signal employed for test purposes is rendered impossible owing to the presence of the interfering spurious signal, which has the advantage that undesired spying out of protected data is precluded.
For the sake of correctness it is to be noted that with an integrated circuit in accordance with the invention it is theoretically also possible to electrically interconnect the conductor track sections, which are in fact required for test purposes, with the aid of a substitute connection, without the additional conductor track sections being included in this electrically conductive substitute connection. However, the effort required in order to realize such an electrically conductive substitute connection is incommensurably greater than the effort required in order to realize such an electrically conductive substitute connection in the case of the integrated circuit known from the patent document DE 42 00 586 A1, as a result of which the fabrication of such an unauthorized substitute connection is now possible almost only in a research laboratory or development laboratory familiar with integration technology, the fabrication of such an unauthorized substitute connection by persons who do not have highly sophisticated equipment at their disposal being no longer possible.
In a method in accordance with the invention and in an integrated circuit in accordance with the invention it has proved to be very advantageous when an additional conductor track section is formed or is present which, together with its adjacent conductor track section, extends up to a bounding surface. Such an embodiment has the great advantage that also in the case that it is attempted to realize a substitute connection in the area of the bounding surface that extends transversely to the semiconductor die of the integrated circuit and in which both the additional conductor track section and the conductor track section adjacent the additional conductor track section, a short-circuit connection is formed between the additional conductor track section and its adjacent conductor track section.
In a method in accordance with the invention and in an integrated circuit in accordance with the invention it has proved to be very advantageous when only one additional conductor track section is formed or is present, which additional conductor track section is situated between the two conductor track sections. This is advantageous in view of a very simple implementation. However, it is to be noted that it is also possible and may be effective to assign an additional conductor track section to each of the two conductor track sections. Furthermore, it is also possible to provide more than one or two additional conductor track sections, i.e. three or more conductor track sections.
The aforementioned aspects as well as further aspects of the invention will be apparent from the examples of embodiments described hereinafter and will be elucidated with the aid of these examples.